Title:
    The JPL Snapdragon Co-Processor
Authors: 
    Zaid Towfic (Jet Propulsion Laboratory, California Institute of Technology)
    Dennis Ogbe (Jet Propulsion Laboratory, California Institute of Technology)
    Saba Janamian (Jet Propulsion Laboratory, California Institute of Technology)
    Andre Jongeling (Jet Propulsion Laboratory, California Institute of Technology)
    Douglas Sheldon (Jet Propulsion Laboratory, California Institute of Technology)
    Joseph Sauvageau (Jet Propulsion Laboratory, California Institute of Technology)
Abstract:
    The Jet Propulsion Laboratory has developed a high-performance co-processor board based on the Qualcomm Snapdragon System-on-Chip (SoC). This board is referred to as the JPL Snapdragon Co-Processor (SCP). The heart of the SCP is the Snapdragon 8155 SoC, which boasts an octa-core CPU complex comprising of quad ARM Cortex A-76 cores and quad ARM Cortex A-55 cores. All CPU cores can support 128-bit NEON vector instructions and the CPU cluster boasts > 100,000 DMIPS compute capability. In addition to the CPU, the SoC also hosts an Adreno 640 graphic processing unit (GPU). The GPU's dual execution units with 384 shaders/unit can deliver nearly 900 GFLOPs of performance at FP32.  Finally, the SoC also hosts a digital signal processor (DSP) that can deliver 7 TOPs. The DSP is highly optimized for quantized neural network inference, FFT computation, among other fixed-point operations. 

    The co-processor board can operate independently, with 128Gbit of onboard memory and 1024Gbit Flash storage, and 2Mbit FRAM. Additionally, the co-processor board provides a variety of interfaces independently of its main connector to a carrier board. These external interfaces include dual USB 3.1 Gen 2 ports (10Gbps each), 4x 4-lane MIPI Camera Serial Interface Connector (40Gbps total/D-PHY v1.2 or 68 Gbps total C-PHY v1.0), as well as a boot select jumper.

    The SCP can be hosted by a variety of carrier cards but has been extensively tested with the JPL Swift carrier card. The internal interfaces to the carrier card from the co-processor board include 2 lane PCIe (16Gbps), 1 lane PCIe (8Gbps), 1x GigE RGMII support, 2x UART, 1x JTAG, 14xGPIO, and 5x SPI/I2C/UART. The Swift carrier card itself hosts a Kintex KU060 Rad Tolerant FPGA, flight interfaces such as Spacewire or RS-422, SerDes interfaces, and its own memory. Additionally, the Kintex FPGA is monitored by a housekeeper RTAX or ProASIC FPGA.

    Both boards (the Swift Carrier Card and the SCP) have passed JPL's TRL-6 assessment process, which assessed both boards for temperature, mechanical (vibration and shock), and radiation effects. Several missions are assessing the use of both boards, including radar and gravitational science missions.